`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: nope
// Engineer: Jose
// 
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: Immediate Generator
// Module Name: imm_gen
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Retrieves the immediate from the instruction (uses verilog concat)
// 
// Dependencies: 
// 
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module imm_gen(
    input  [31:0] inst_in,
    output reg [31:0] imm_out
);

always @(*) begin 
    case(inst_in[6:0]) 
        // Formato I
        7'b0010011, 
        7'b0000011,
        7'b1100111:
            imm_out = {{20{inst_in[31]}}, inst_in[31:20]};

        // Formato S
        7'b0100011:
            imm_out = {{20{inst_in[31]}}, inst_in[31:25], inst_in[11:7]};

        // Formato B
        7'b1100011:
            imm_out = {{19{inst_in[31]}}, inst_in[31], inst_in[7], inst_in[30:25], inst_in[11:8], 1'b0};

        // Formato J
        7'b1101111:
            imm_out = {{11{inst_in[31]}}, inst_in[31], inst_in[19:12], inst_in[20], inst_in[30:21], 1'b0};

        // Formato U
        7'b0110111, 
        7'b0010111:
            imm_out = {inst_in[31:12], 12'b0};

        default:
            imm_out = 32'b0;
    endcase
end

endmodule