`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: nope
// Engineer: Jose
// 
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: IF/ID register
// Module Name: if_id
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Register between IF/ID stages
// 
// Dependencies: 
// 
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module if_id (
    input clk,
    input rst,
    input en,
    input clr,
    input [31:0] pc_in,
    input [31:0] pc4_in,
    input [31:0] inst_in,
    output reg [31:0] pc_out,
    output reg [31:0] pc4_out,
    output reg [31:0] inst_out
);

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            pc_out <= 32'b0;
            pc4_out <= 32'b0;
            inst_out  <= 32'b0;
        end else if (clr) begin
            pc_out <= 32'b0;
            pc4_out <= 32'b0;
            inst_out  <= 32'b0; 
        end else if (en) begin
            pc_out <= pc_in;
            pc4_out <= pc4_in;
            inst_out  <= inst_in;
        end
    end
endmodule