`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: nope
// Engineer: Jose
// 
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: Instruction Memory
// Module Name: imem
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Stores instructions
// 
// Dependencies: 
// 
// Revision: 2.0 - Dual port for UART programming
// Revision: 1.0 - Basic structure
// Revision: 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module imem(
    input clk,
    
    // puerto 1
    input [31:0] read_addr,
    output [31:0] inst_out,
    
    // puerto 2
    input we_ext,
    input [31:0] write_addr_ext,
    input [31:0] write_data_ext
);

reg [31:0] memory[0:255];
reg [31:0] inst_reg;

integer i;
initial begin
    for (i = 0; i < 256; i = i + 1) begin
        memory[i] = 32'b0;
    end
end

always @(posedge clk) begin
    if(we_ext) begin 
        memory[write_addr_ext[9:2]] <= write_data_ext;
    end
        
    inst_reg <= memory[read_addr[9:2]];
end

assign inst_out = inst_reg;

endmodule