`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: 
// Module Name: alu
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module alu(
     input [31:0] A, B,
     input [3:0] sel,
     output reg [31:0] R,
     output zero
);

always @(*) begin
    case(sel)
        4'b0000: R <= A + B;               // add
        4'b0001: R <= A - B;               // sub
        4'b0010: R <= A & B;               // and
        4'b0011: R <= A | B;               // or
        4'b0100: R <= A ^ B;               // xor
        4'b0101: R <= A << B[4:0];         // sll (shamt = 5 bits)
        4'b0110: R <= A >> B[4:0];         // srl (logical)
        4'b0111: R <= ($signed(A) < $signed(B)) ? 1 : 0; // slt signed
        4'b1000: R <= (A < B) ? 1 : 0;     // sltu unsigned
        4'b1001: R <= $signed(A) >>> B[4:0]; // sra arithmetic right
        4'b1010: R <= 32'b0;               // default / nop opcional
        default: R <= 32'b0;
    endcase
end

assign zero = (R == 0);

endmodule