`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: nope
// Engineer: Jose
// 
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: Data Memory
// Module Name: dmem
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Stores data
// 
// Dependencies: 
// 
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module dmem(
    input clk,
    input we,
    input [31:0] address,
    input [31:0] write_data,
    output [31:0] mem_data_out
);

reg [31:0] memory[0:255];
reg [31:0] data_reg;

integer i;
initial begin
    for (i = 0; i < 256; i = i + 1) begin
        memory[i] = 32'b0;
    end
end

always @(posedge clk) begin
    if (we)
        memory[address[9:2]] <= write_data;
    data_reg <= memory[address[9:2]];
end

assign mem_data_out = data_reg;

endmodule