Gallardo7761/riscv-ac
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add: uart_tx module

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This commit is contained in:
Jose
2026-03-03 03:41:56 +01:00
parent a890b031a7
commit a4b158d6a8
39 changed files with 492 additions and 60 deletions
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44
riscv-ac.srcs/sources_1/new/top.v
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@@ -30,11 +30,32 @@ module top (
input prog_we,
// Debug & UART
input rx,
output tx,
output [1:0] leds,
output [31:0] uart_tx_data,
output [7:0] uart_tx_data,
output uart_tx_en
);
// ==========================================
// BOOTLOADER
// ==========================================
wire [31:0] prog_data;
wire [31:0] prog_addr;
wire prog_we;
wire boot_rst;
uart_bootloader u_boot (
.clk(clk),
.rx(rx),
.prog_data(prog_data),
.prog_addr(prog_addr),
.prog_we(prog_we),
.cpu_rst(boot_rst)
);
wire sys_rst = rst | boot_rst;
// ==========================================
// ETAPA IF
// ==========================================
@@ -47,7 +68,7 @@ module top (
pc u_pc (
.clk(clk),
.rst(rst),
.rst(sys_rst),
.next_pc(pc_stall),
.pc_out(npc_IF)
);
@@ -55,7 +76,7 @@ module top (
imem u_imem (
.clk(clk),
// por aqui lee la CPU
.read_addr(pc_IF),
.read_addr(npc_IF),
.inst_out(ir_IF),
// por aqui meto el programa
.we_ext(prog_we),
@@ -69,7 +90,7 @@ module top (
wire [31:0] npc_ID, pc4_ID, ir_ID;
if_id u_if_id (
.clk(clk), .rst(rst), .en(IF_ID_En), .clr(IF_ID_Clr),
.clk(clk), .rst(sys_rst), .en(IF_ID_En), .clr(IF_ID_Clr),
.pc_in(npc_IF), .pc4_in(pc4_IF), .inst_in(ir_IF),
.pc_out(npc_ID), .pc4_out(pc4_ID), .inst_out(ir_ID)
);
@@ -137,7 +158,7 @@ module top (
wire [3:0] alu_op_EX;
id_ex u_id_ex (
.clk(clk), .rst(rst), .clr(ID_EX_Clr),
.clk(clk), .rst(sys_rst), .clr(ID_EX_Clr),
.we_reg_in(we_reg_ID), .we_mem_in(we_mem_ID), .mem_to_reg_in(mem_to_reg_ID),
.alu_src_in(alu_src_ID), .branch_in(branch_ID), .alu_op_in(alu_op_ID),
.jump_in(jump_ID),
@@ -184,7 +205,7 @@ module top (
wire we_reg_ME, we_mem_ME, mem_to_reg_ME;
ex_me u_ex_me (
.clk(clk), .rst(rst),
.clk(clk), .rst(sys_rst),
.we_reg_in(we_reg_EX), .we_mem_in(we_mem_EX), .mem_to_reg_in(mem_to_reg_EX),
.we_reg_out(we_reg_ME), .we_mem_out(we_mem_ME), .mem_to_reg_out(mem_to_reg_ME),
.alu_in(alu_res_EX), .regB_in(alu_B_temp), .pc4_in(pc4_EX), .rd_in(rd_EX),
@@ -200,7 +221,14 @@ module top (
wire dmem_we = we_mem_ME & ~is_uart; // si va pa la UART no escribimos en memoria
assign uart_tx_en = we_mem_ME & is_uart;
assign uart_tx_data = regB_ME;
assign uart_tx_data = regB_ME[7:0];
uart_tx u_tx (
.clk(clk),
.data_in(uart_tx_data),
.tx_en(uart_tx_en),
.tx(tx)
);
// --------------------------------------------------------------
wire [31:0] mem_data_ME;
@@ -214,7 +242,7 @@ module top (
wire we_reg_WB, mem_to_reg_WB;
me_wb u_me_wb (
.clk(clk), .rst(rst),
.clk(clk), .rst(sys_rst),
.we_reg_in(we_reg_ME), .mem_to_reg_in(mem_to_reg_ME),
.we_reg_out(we_reg_WB), .mem_to_reg_out(mem_to_reg_WB),
.alu_in(alu_res_ME), .mem_data_in(mem_data_ME), .pc4_in(pc4_ME), .rd_in(rd_ME),