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add: uart_tx module

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Jose
2026-03-03 03:41:56 +01:00
parent a890b031a7
commit a4b158d6a8
39 changed files with 492 additions and 60 deletions
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52
riscv-ac.srcs/sim_1/new/tb_top.v
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@@ -26,13 +26,18 @@
module tb_top();
reg clk;
reg rst;
wire [1:0] leds;
wire [31:0] uart_tx_data;
wire [7:0] uart_tx_data;
wire uart_tx_en;
reg rx;
wire tx;
top uut (
.clk(clk),
.rst(rst),
.rx(rx),
.tx(tx),
.leds(leds),
.uart_tx_data(uart_tx_data),
.uart_tx_en(uart_tx_en)
@@ -40,21 +45,58 @@ module tb_top();
// T_CLK = 10ns
always #5 clk = ~clk;
task send_uart_byte;
input [7:0] data;
integer i;
begin
// 1. Bit de Start (bajamos a 0)
rx = 0;
#(868 * 10); // Esperamos los ciclos de 1 bit (104 ciclos * 10ns)
// 2. Mandamos los 8 bits de datos (LSB primero, de derecha a izquierda)
for (i = 0; i < 8; i = i + 1) begin
rx = data[i];
#(868 * 10);
end
// 3. Bit de Stop (subimos a 1)
rx = 1;
#(868 * 10);
end
endtask
initial begin
// inicializamos señales
clk = 0;
rst = 1;
rx = 1;
// cargamos programa
$readmemh("/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/program.mem", uut.u_imem.memory);
// (SOLO SIMULACION) cargamos programa
//$readmemh("/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/program.mem", uut.u_imem.memory);
// activamos reset 20ns
#20;
rst = 0;
// ejecución de 100 ciclos
#150;
// mandamos instrucciones
#100;
// 1. addi x5, x0, 65 (04100293) -> cargamos 'A' (65) en x5
send_uart_byte(8'h93); send_uart_byte(8'h02); send_uart_byte(8'h10); send_uart_byte(8'h04);
// 2. addi x6, x0, -4 (ffc00313) -> cargamos la dirección de la UART mapeada (0xFFFFFFFC) en x6
send_uart_byte(8'h13); send_uart_byte(8'h03); send_uart_byte(8'hC0); send_uart_byte(8'hFF);
// 3. sw x5, 0(x6) (00532023) -> alla que va pa la UART
send_uart_byte(8'h23); send_uart_byte(8'h20); send_uart_byte(8'h53); send_uart_byte(8'h00);
// 4. jal x0, 0 (0000006f) -> fin
send_uart_byte(8'h6F); send_uart_byte(8'h00); send_uart_byte(8'h00); send_uart_byte(8'h00);
#(55000 * 10)
#2000;
$finish;
end