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add: uart_tx module

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This commit is contained in:
Jose
2026-03-03 03:41:56 +01:00
parent a890b031a7
commit a4b158d6a8
39 changed files with 492 additions and 60 deletions
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68
riscv-ac.srcs/constrs_1/new/CmodA7_Master.xdc
View File

@@ -43,38 +43,38 @@ set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { rst }]
## GPIO Pins
## Pins 15 and 16 should remain commented if using them as analog inputs
set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { debug[0] }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports { debug[1] }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { debug[2] }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports { debug[3] }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { debug[4] }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { debug[5] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { debug[6] }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { debug[7] }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]
set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { debug[8] }]; #IO_L6P_T0_16 Sch=pio[09]
set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { debug[9] }]; #IO_L7P_T1_AD6P_35 Sch=pio[10]
set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports { debug[10] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11]
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { debug[11] }]; #IO_L5P_T0_AD13P_35 Sch=pio[12]
set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports { debug[12] }]; #IO_L6N_T0_VREF_35 Sch=pio[13]
set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports { debug[13] }]; #IO_L5N_T0_AD13N_35 Sch=pio[14]
set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports { debug[14] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17]
set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports { debug[15] }]; #IO_L12P_T1_MRCC_35 Sch=pio[18]
set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { debug[16] }]; #IO_L12N_T1_MRCC_35 Sch=pio[19]
set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports { debug[17] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20]
set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports { debug[18] }]; #IO_L10N_T1_AD15N_35 Sch=pio[21]
set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports { debug[19] }]; #IO_L10P_T1_AD15P_35 Sch=pio[22]
set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { debug[20] }]; #IO_L19N_T3_VREF_35 Sch=pio[23]
set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { debug[21] }]; #IO_L2P_T0_34 Sch=pio[26]
set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports { debug[22] }]; #IO_L2N_T0_34 Sch=pio[27]
set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports { debug[23] }]; #IO_L1P_T0_34 Sch=pio[28]
set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports { debug[24] }]; #IO_L3P_T0_DQS_34 Sch=pio[29]
set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports { debug[25] }]; #IO_L1N_T0_34 Sch=pio[30]
set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports { debug[26] }]; #IO_L3N_T0_DQS_34 Sch=pio[31]
set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports { debug[27] }]; #IO_L5N_T0_34 Sch=pio[32]
set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports { debug[28] }]; #IO_L5P_T0_34 Sch=pio[33]
set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports { debug[29] }]; #IO_L6N_T0_VREF_34 Sch=pio[34]
set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { debug[30] }]; #IO_L6P_T0_34 Sch=pio[35]
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { debug[31] }]; #IO_L12P_T1_MRCC_34 Sch=pio[36]
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { pio }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports { data_out[0] }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { data_out[1] }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports { data_out[2] }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { data_out[3] }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { pio[06] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { pio[07] }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { pio[08] }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { pio[09] }]; #IO_L6P_T0_16 Sch=pio[09]
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { pio[10] }]; #IO_L7P_T1_AD6P_35 Sch=pio[10]
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports { pio[11] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11]
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { pio[12] }]; #IO_L5P_T0_AD13P_35 Sch=pio[12]
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports { pio[13] }]; #IO_L6N_T0_VREF_35 Sch=pio[13]
#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports { pio[14] }]; #IO_L5N_T0_AD13N_35 Sch=pio[14]
#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports { pio[17] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17]
#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports { pio[18] }]; #IO_L12P_T1_MRCC_35 Sch=pio[18]
#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { pio[19] }]; #IO_L12N_T1_MRCC_35 Sch=pio[19]
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports { pio[20] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20]
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports { pio[21] }]; #IO_L10N_T1_AD15N_35 Sch=pio[21]
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports { pio[22] }]; #IO_L10P_T1_AD15P_35 Sch=pio[22]
#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { pio[23] }]; #IO_L19N_T3_VREF_35 Sch=pio[23]
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { pio[26] }]; #IO_L2P_T0_34 Sch=pio[26]
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports { pio[27] }]; #IO_L2N_T0_34 Sch=pio[27]
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports { pio[28] }]; #IO_L1P_T0_34 Sch=pio[28]
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports { pio[29] }]; #IO_L3P_T0_DQS_34 Sch=pio[29]
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports { pio[30] }]; #IO_L1N_T0_34 Sch=pio[30]
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports { pio[31] }]; #IO_L3N_T0_DQS_34 Sch=pio[31]
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports { pio[32] }]; #IO_L5N_T0_34 Sch=pio[32]
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports { pio[33] }]; #IO_L5P_T0_34 Sch=pio[33]
#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports { pio[34] }]; #IO_L6N_T0_VREF_34 Sch=pio[34]
#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { pio[35] }]; #IO_L6P_T0_34 Sch=pio[35]
#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { pio[36] }]; #IO_L12P_T1_MRCC_34 Sch=pio[36]
#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports { pio[37] }]; #IO_L11N_T1_SRCC_34 Sch=pio[37]
#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports { pio[38] }]; #IO_L11P_T1_SRCC_34 Sch=pio[38]
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { pio[39] }]; #IO_L16N_T2_34 Sch=pio[39]
@@ -90,8 +90,8 @@ set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { debug[
## UART
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { tx }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { rx }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
## Crypto 1 Wire Interface

52
riscv-ac.srcs/sim_1/new/tb_top.v
View File

@@ -26,13 +26,18 @@
module tb_top();
reg clk;
reg rst;
wire [1:0] leds;
wire [31:0] uart_tx_data;
wire [7:0] uart_tx_data;
wire uart_tx_en;
reg rx;
wire tx;
top uut (
.clk(clk),
.rst(rst),
.rx(rx),
.tx(tx),
.leds(leds),
.uart_tx_data(uart_tx_data),
.uart_tx_en(uart_tx_en)
@@ -40,21 +45,58 @@ module tb_top();
// T_CLK = 10ns
always #5 clk = ~clk;
task send_uart_byte;
input [7:0] data;
integer i;
begin
// 1. Bit de Start (bajamos a 0)
rx = 0;
#(868 * 10); // Esperamos los ciclos de 1 bit (104 ciclos * 10ns)
// 2. Mandamos los 8 bits de datos (LSB primero, de derecha a izquierda)
for (i = 0; i < 8; i = i + 1) begin
rx = data[i];
#(868 * 10);
end
// 3. Bit de Stop (subimos a 1)
rx = 1;
#(868 * 10);
end
endtask
initial begin
// inicializamos señales
clk = 0;
rst = 1;
rx = 1;
// cargamos programa
$readmemh("/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/program.mem", uut.u_imem.memory);
// (SOLO SIMULACION) cargamos programa
//$readmemh("/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/program.mem", uut.u_imem.memory);
// activamos reset 20ns
#20;
rst = 0;
// ejecución de 100 ciclos
#150;
// mandamos instrucciones
#100;
// 1. addi x5, x0, 65 (04100293) -> cargamos 'A' (65) en x5
send_uart_byte(8'h93); send_uart_byte(8'h02); send_uart_byte(8'h10); send_uart_byte(8'h04);
// 2. addi x6, x0, -4 (ffc00313) -> cargamos la dirección de la UART mapeada (0xFFFFFFFC) en x6
send_uart_byte(8'h13); send_uart_byte(8'h03); send_uart_byte(8'hC0); send_uart_byte(8'hFF);
// 3. sw x5, 0(x6) (00532023) -> alla que va pa la UART
send_uart_byte(8'h23); send_uart_byte(8'h20); send_uart_byte(8'h53); send_uart_byte(8'h00);
// 4. jal x0, 0 (0000006f) -> fin
send_uart_byte(8'h6F); send_uart_byte(8'h00); send_uart_byte(8'h00); send_uart_byte(8'h00);
#(55000 * 10)
#2000;
$finish;
end

44
riscv-ac.srcs/sources_1/new/top.v
View File

@@ -30,11 +30,32 @@ module top (
input prog_we,
// Debug & UART
input rx,
output tx,
output [1:0] leds,
output [31:0] uart_tx_data,
output [7:0] uart_tx_data,
output uart_tx_en
);
// ==========================================
// BOOTLOADER
// ==========================================
wire [31:0] prog_data;
wire [31:0] prog_addr;
wire prog_we;
wire boot_rst;
uart_bootloader u_boot (
.clk(clk),
.rx(rx),
.prog_data(prog_data),
.prog_addr(prog_addr),
.prog_we(prog_we),
.cpu_rst(boot_rst)
);
wire sys_rst = rst | boot_rst;
// ==========================================
// ETAPA IF
// ==========================================
@@ -47,7 +68,7 @@ module top (
pc u_pc (
.clk(clk),
.rst(rst),
.rst(sys_rst),
.next_pc(pc_stall),
.pc_out(npc_IF)
);
@@ -55,7 +76,7 @@ module top (
imem u_imem (
.clk(clk),
// por aqui lee la CPU
.read_addr(pc_IF),
.read_addr(npc_IF),
.inst_out(ir_IF),
// por aqui meto el programa
.we_ext(prog_we),
@@ -69,7 +90,7 @@ module top (
wire [31:0] npc_ID, pc4_ID, ir_ID;
if_id u_if_id (
.clk(clk), .rst(rst), .en(IF_ID_En), .clr(IF_ID_Clr),
.clk(clk), .rst(sys_rst), .en(IF_ID_En), .clr(IF_ID_Clr),
.pc_in(npc_IF), .pc4_in(pc4_IF), .inst_in(ir_IF),
.pc_out(npc_ID), .pc4_out(pc4_ID), .inst_out(ir_ID)
);
@@ -137,7 +158,7 @@ module top (
wire [3:0] alu_op_EX;
id_ex u_id_ex (
.clk(clk), .rst(rst), .clr(ID_EX_Clr),
.clk(clk), .rst(sys_rst), .clr(ID_EX_Clr),
.we_reg_in(we_reg_ID), .we_mem_in(we_mem_ID), .mem_to_reg_in(mem_to_reg_ID),
.alu_src_in(alu_src_ID), .branch_in(branch_ID), .alu_op_in(alu_op_ID),
.jump_in(jump_ID),
@@ -184,7 +205,7 @@ module top (
wire we_reg_ME, we_mem_ME, mem_to_reg_ME;
ex_me u_ex_me (
.clk(clk), .rst(rst),
.clk(clk), .rst(sys_rst),
.we_reg_in(we_reg_EX), .we_mem_in(we_mem_EX), .mem_to_reg_in(mem_to_reg_EX),
.we_reg_out(we_reg_ME), .we_mem_out(we_mem_ME), .mem_to_reg_out(mem_to_reg_ME),
.alu_in(alu_res_EX), .regB_in(alu_B_temp), .pc4_in(pc4_EX), .rd_in(rd_EX),
@@ -200,7 +221,14 @@ module top (
wire dmem_we = we_mem_ME & ~is_uart; // si va pa la UART no escribimos en memoria
assign uart_tx_en = we_mem_ME & is_uart;
assign uart_tx_data = regB_ME;
assign uart_tx_data = regB_ME[7:0];
uart_tx u_tx (
.clk(clk),
.data_in(uart_tx_data),
.tx_en(uart_tx_en),
.tx(tx)
);
// --------------------------------------------------------------
wire [31:0] mem_data_ME;
@@ -214,7 +242,7 @@ module top (
wire we_reg_WB, mem_to_reg_WB;
me_wb u_me_wb (
.clk(clk), .rst(rst),
.clk(clk), .rst(sys_rst),
.we_reg_in(we_reg_ME), .mem_to_reg_in(mem_to_reg_ME),
.we_reg_out(we_reg_WB), .mem_to_reg_out(mem_to_reg_WB),
.alu_in(alu_res_ME), .mem_data_in(mem_data_ME), .pc4_in(pc4_ME), .rd_in(rd_ME),

255
riscv-ac.srcs/sources_1/new/uart_bootloader.v Normal file
View File

@@ -0,0 +1,255 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: nope
// Engineer: Jose
//
// Create Date: 03/03/2026 02:40:56 AM
// Design Name: Bootloader
// Module Name: uart_bootloader
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Allows dynamic program burning
//
// Dependencies:
//
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_bootloader (
input wire clk, // Reloj de la placa (12 MHz)
input wire rx, // Cable de entrada de datos desde el USB
output reg [31:0] prog_data, // Instrucción completa de 32 bits
output reg [31:0] prog_addr, // Dirección donde vamos a guardarla
output reg prog_we, // Señal para escribir en la imem
output wire cpu_rst // Mantiene al RISC-V en reset mientras programamos
);
// Parámetros para 12 MHz y 115200 baudios
// 12.000.000 / 115200 = 104 ciclos por bit
localparam CLKS_PER_BIT = 104;
// 1 segundo de timeout a 12 MHz para soltar el reset
localparam TIMEOUT_LIMIT = 12_000_000;
// Estados de la máquina UART RX
localparam S_IDLE = 2'b00;
localparam S_START = 2'b01;
localparam S_DATA = 2'b10;
localparam S_STOP = 2'b11;
reg [1:0] state = S_IDLE;
reg [7:0] clk_count = 0;
reg [2:0] bit_index = 0;
reg [7:0] rx_byte = 0;
reg rx_done = 0;
// --- 1. MÁQUINA DE ESTADOS UART RX ---
always @(posedge clk) begin
rx_done <= 0;
case (state)
S_IDLE: begin
clk_count <= 0;
bit_index <= 0;
if (rx == 1'b0) // Detectamos el Start Bit (baja a 0)
state <= S_START;
end
S_START: begin
if (clk_count == (CLKS_PER_BIT / 2)) begin
if (rx == 1'b0) begin // Confirmamos que es un Start bit válido
clk_count <= 0;
state <= S_DATA;
end else
state <= S_IDLE;
end else
clk_count <= clk_count + 1;
end
S_DATA: begin
if (clk_count == CLKS_PER_BIT - 1) begin
clk_count <= 0;
rx_byte[bit_index] <= rx; // Guardamos el bit
if (bit_index == 7) begin
bit_index <= 0;
state <= S_STOP;
end else
bit_index <= bit_index + 1;
end else
clk_count <= clk_count + 1;
end
S_STOP: begin
if (clk_count == CLKS_PER_BIT - 1) begin
rx_done <= 1; // ¡Byte recibido de lujo!
state <= S_IDLE;
end else
clk_count <= clk_count + 1;
end
endcase
end
// --- 2. ENSAMBLADOR DE 32 BITS Y CONTROL DE TIMEOUT ---
reg [1:0] byte_count = 0;
reg [23:0] timeout_counter = 0;
reg is_programming = 1; // Empezamos en modo programación por defecto
// El procesador está en reset (apagado) mientras is_programming sea 1
assign cpu_rst = is_programming;
always @(posedge clk) begin
prog_we <= 0; // Por defecto no escribimos
if (rx_done) begin
// Ha llegado un byte nuevo, reseteamos el timeout
timeout_counter <= 0;
is_programming <= 1;
// RISC-V usa Little Endian (el byte menos significativo llega primero)
prog_data <= {rx_byte, prog_data[31:8]};
if (byte_count == 3) begin
byte_count <= 0;
prog_we <= 1; // ¡Tenemos los 32 bits! Damos la orden de escribir
// Avanzamos la dirección para la siguiente instrucción (después de escribir)
end else begin
byte_count <= byte_count + 1;
end
end else begin
// Si acabamos de escribir, subimos la dirección
if (prog_we) begin
prog_addr <= prog_addr + 4;
end
// Control de timeout (perro guardián)
if (is_programming) begin
if (timeout_counter == TIMEOUT_LIMIT) begin
is_programming <= 0; // ¡Se acabó el tiempo! Soltamos al procesador
prog_addr <= 0; // Reseteamos el puntero para la próxima vez
byte_count <= 0;
end else begin
timeout_counter <= timeout_counter + 1;
end
end
end
end
endmodule`timescale 1ns / 1ps
`default_nettype none
module uart_bootloader (
input wire clk, // reloj de la placa (12 MHz)
input wire rx, // cable de entrada de datos desde el USB
output reg [31:0] prog_data = 0, // instrucción completa de 32 bits
output reg [31:0] prog_addr = 0, // dirección donde vamos a guardarla
output reg prog_we, // señal para escribir en la imem
output wire cpu_rst // mantiene el CPU en reset mientras programamos
);
// parámetros para 12 MHz y 115200 de baudrate
// 12e6 / 115200 = 104 ciclos por bit
// 1 segundo de timeout a 12 MHz para soltar el reset
localparam CLKS_PER_BIT = 104; // 868;
localparam TIMEOUT_LIMIT = 12_000_000; // 50000;
localparam S_IDLE = 2'b00;
localparam S_START = 2'b01;
localparam S_DATA = 2'b10;
localparam S_STOP = 2'b11;
reg [1:0] state = S_IDLE;
reg [15:0] clk_count = 0;
reg [2:0] bit_index = 0;
reg [7:0] rx_byte = 0;
reg rx_done = 0;
reg [1:0] byte_count = 0;
reg [23:0] timeout_counter = 0;
reg is_programming = 1;
// FSM de la UART
always @(posedge clk) begin
rx_done <= 0;
case (state)
S_IDLE: begin
clk_count <= 0;
bit_index <= 0;
if (rx == 1'b0)
state <= S_START;
end
S_START: begin
if (clk_count == (CLKS_PER_BIT / 2)) begin
if (rx == 1'b0) begin
clk_count <= 0;
state <= S_DATA;
end else
state <= S_IDLE;
end else
clk_count <= clk_count + 1;
end
S_DATA: begin
if (clk_count == CLKS_PER_BIT - 1) begin
clk_count <= 0;
rx_byte[bit_index] <= rx;
if (bit_index == 7) begin
bit_index <= 0;
state <= S_STOP;
end else
bit_index <= bit_index + 1;
end else
clk_count <= clk_count + 1;
end
S_STOP: begin
if (clk_count == CLKS_PER_BIT - 1) begin
rx_done <= 1; // byte recibido
state <= S_IDLE;
end else
clk_count <= clk_count + 1;
end
endcase
end
assign cpu_rst = is_programming;
always @(posedge clk) begin
prog_we <= 0;
if (rx_done) begin
// byte nuevo
timeout_counter <= 0;
is_programming <= 1;
// little-endian
prog_data <= {rx_byte, prog_data[31:8]};
if (byte_count == 3) begin
byte_count <= 0;
prog_we <= 1; // 32b han llegado, escribimos
end else begin
byte_count <= byte_count + 1;
end
end else begin
if (prog_we) begin
prog_addr <= prog_addr + 4;
end
if (is_programming) begin
if (timeout_counter == TIMEOUT_LIMIT) begin
is_programming <= 0; // timeout excedido, soltamos CPU
prog_addr <= 0; // reset al puntero
byte_count <= 0;
end else begin
timeout_counter <= timeout_counter + 1;
end
end
end
end
endmodule

89
riscv-ac.srcs/sources_1/new/uart_tx.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: nope
// Engineer: Jose
//
// Create Date: 03/03/2026 03:02:49 AM
// Design Name: UART TX Module
// Module Name: uart_tx
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Allows UART transmission
//
// Dependencies:
//
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_tx (
input wire clk,
input wire [7:0] data_in,
input wire tx_en,
output reg tx = 1
);
// 12e6 / 115200 = 104 ciclos
localparam CLKS_PER_BIT = 104; // 104;
localparam S_IDLE = 2'b00;
localparam S_START = 2'b01;
localparam S_DATA = 2'b10;
localparam S_STOP = 2'b11;
reg [1:0] state = S_IDLE;
reg [15:0] clk_count = 0;
reg [2:0] bit_index = 0;
reg [7:0] tx_data = 0;
always @(posedge clk) begin
case (state)
S_IDLE: begin
tx <= 1;
clk_count <= 0;
bit_index <= 0;
if (tx_en) begin
tx_data <= data_in;
state <= S_START;
end
end
S_START: begin
tx <= 0;
if (clk_count < CLKS_PER_BIT - 1) begin
clk_count <= clk_count + 1;
end else begin
clk_count <= 0;
state <= S_DATA;
end
end
S_DATA: begin
tx <= tx_data[bit_index];
if (clk_count < CLKS_PER_BIT - 1) begin
clk_count <= clk_count + 1;
end else begin
clk_count <= 0;
if (bit_index == 7) begin
state <= S_STOP;
end else begin
bit_index <= bit_index + 1;
end
end
end
S_STOP: begin
tx <= 1;
if (clk_count < CLKS_PER_BIT - 1) begin
clk_count <= clk_count + 1;
end else begin
state <= S_IDLE;
end
end
endcase
end
endmodule