add: uart_tx module

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Jose

2026-03-03 03:41:56 +01:00

parent a890b031a7

commit a4b158d6a8

39 changed files with 492 additions and 60 deletions

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riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb

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