add: uart_tx module

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

@@ -3,7 +3,7 @@
 Nov 14 2025
 12:36:23
 /home/jomaa/git/riscv-ac/riscv-ac.sim/sim_1/behav/xsim/glbl.v,1756381829,verilog,,,,glbl,,,,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,1772486573,verilog,,,,tb_top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,1772504151,verilog,,,,tb_top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/alu.v,1772490502,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,,alu,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,1772486779,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,,control,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,1772490163,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,,dmem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
@@ -12,9 +12,11 @@ Nov 14 2025
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,1772467244,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,,hazard,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,1772490462,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,,id_ex,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,1772490110,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,,if_id,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,1772490099,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,,imem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,1772496962,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,,imem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772490121,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772468767,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,1772289140,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,,pc,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772490599,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,1772490088,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,,pc,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
 /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,1772483280,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,,regfile,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,1772486142,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,,top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,1772503421,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,,top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,1772505234,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_tx.v,,uart_bootloader,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_tx.v,1772503459,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,,uart_tx,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,