add: uart_tx module

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx

@@ -1,6 +1,6 @@
 
 { 
-    crc :  899746931471304080  , 
+    crc :  7757595850083595454  , 
     ccp_crc :  0  , 
     cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl" , 
     buildDate : "Nov 14 2025" , 

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini

@@ -25,11 +25,11 @@ INOUT_PROTOINST_FILTER=true
 INTERNAL_PROTOINST_FILTER=true
 CONSTANT_PROTOINST_FILTER=true
 VARIABLE_PROTOINST_FILTER=true
-SCOPE_NAME_COLUMN_WIDTH=159
+SCOPE_NAME_COLUMN_WIDTH=93
 SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83
 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
-OBJECT_NAME_COLUMN_WIDTH=154
-OBJECT_VALUE_COLUMN_WIDTH=1904
+OBJECT_NAME_COLUMN_WIDTH=147
+OBJECT_VALUE_COLUMN_WIDTH=49
 OBJECT_DATA_TYPE_COLUMN_WIDTH=75
 PROCESS_NAME_COLUMN_WIDTH=75
 PROCESS_TYPE_COLUMN_WIDTH=75