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add: uart_tx module

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Jose
2026-03-03 03:41:56 +01:00
parent a890b031a7
commit a4b158d6a8
39 changed files with 492 additions and 60 deletions
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riscv-ac.sim/sim_1/behav/xsim/tb_top_vlog.prj
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@@ -14,6 +14,8 @@ verilog xil_defaultlib --include "../../../../../../../../opt/Xilinx/2025.2/dat
"../../../../riscv-ac.srcs/sources_1/new/pc.v" \
"../../../../riscv-ac.srcs/sources_1/new/regfile.v" \
"../../../../riscv-ac.srcs/sources_1/new/top.v" \
"../../../../riscv-ac.srcs/sources_1/new/uart_bootloader.v" \
"../../../../riscv-ac.srcs/sources_1/new/uart_tx.v" \
"../../../../riscv-ac.srcs/sim_1/new/tb_top.v" \
# compile glbl module