# compile verilog/system verilog design source files
verilog xil_defaultlib  --include "../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef" \
"../../../../riscv-ac.srcs/sources_1/new/alu.v" \
"../../../../riscv-ac.srcs/sources_1/new/control.v" \
"../../../../riscv-ac.srcs/sources_1/new/dmem.v" \
"../../../../riscv-ac.srcs/sources_1/new/ex_me.v" \
"../../../../riscv-ac.srcs/sources_1/new/forwarding.v" \
"../../../../riscv-ac.srcs/sources_1/new/hazard.v" \
"../../../../riscv-ac.srcs/sources_1/new/id_ex.v" \
"../../../../riscv-ac.srcs/sources_1/new/if_id.v" \
"../../../../riscv-ac.srcs/sources_1/new/imem.v" \
"../../../../riscv-ac.srcs/sources_1/new/imm_gen.v" \
"../../../../riscv-ac.srcs/sources_1/new/me_wb.v" \
"../../../../riscv-ac.srcs/sources_1/new/pc.v" \
"../../../../riscv-ac.srcs/sources_1/new/regfile.v" \
"../../../../riscv-ac.srcs/sources_1/new/top.v" \
"../../../../riscv-ac.srcs/sources_1/new/uart_bootloader.v" \
"../../../../riscv-ac.srcs/sources_1/new/uart_tx.v" \
"../../../../riscv-ac.srcs/sim_1/new/tb_top.v" \

# compile glbl module
verilog xil_defaultlib "glbl.v"

# Do not sort compile order
nosort
